CSE Colloquium: A frontend for all workloads

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 ABSTRACT: Thanks to Moore's law, today's processors comprise billions of transistors. With the end of Moore's Law, the focus must turn toward using this abundance of transistors more effectively. The first part of this talk describes AsmDB, a fleet-wide study of Google workloads. Among the many findings, AsmDB highlights gross inefficiencies in processor frontends resulting from application working sets exceeding instruction cache capacities. The second part of this talk describes Emissary, a new approach to mitigate this problem by using available cache capacity more efficiently. Observing that not all cache misses cause stalls, Emissary employs a novel cache replacement algorithm that reserves cache capacity for lines whose misses cause the greatest performance impact. When implemented in the first-level instruction cache, Emissary outperforms all known cache replacement algorithms in both performance and energy consumption. In some cases, it produces speedups that exceed Belady's OPT, the perfect-knowledge minimal-miss ideal cache replacement algorithm. This talk concludes with an outline of future research directions to further improve processor performance and efficiency in the post-Moore's law era. 

BIOGRAPHY: Nayana is a Ph.D. candidate at Princeton University, advised by Prof. David August. Her research interests are in the field of computer architecture, microarchitecture, memory system, and hardware/software co-design. Her Ph.D. dissertation is focused on characterizing and reducing the frontend stalls for all workloads. To that end, she designed novel cache replacement techniques to improve the CPU performance. In 2020, she received an IEEE MICRO "Top Picks" for her frontend work. Before joining Princeton, Nayana worked at AMD, Bangalore, as a Power Management Verification Engineer, and she earned her Master's degree in Embedded Systems Engineering from the University of Leeds, U.K. in 2010.