Designing OS and Hardware Constructs for Next-Generation High-End Systems

Zoom info: https://psu.zoom.us/j/93071016619?pwd=YVRRd2ZmMWtQcHE4NnF4Qnk4NjJaQT09

Abstract: Modern high-end systems are becoming increasingly diverse, having already transitioned from single-core to multi-core to many-core systems employing accelerators like GPUs and TPUs. On the memory front, emerging memory technologies like 3D stacked DRAMs, Non-Volatile memories, and disaggregated Fabric Attached Memories are further broadening and diversifying the memory landscape. Additionally, workloads in HPC and Cloud environments have been continuously emerging ranging from ubiquitous Machine Learning to Genome Sequencing to irregular Graph Analytics. Current computer system abstractions that are built in the era of scarce compute (single core) and scarce memory (several hundred MBs of DRAM capacity) are quickly imposing severe performance/scalability bottlenecks in high-end HPC and data center systems. These emerging workloads and hardware require re-designing the OS and hardware constructs holistically. The emerging vulnerabilities in Cloud scenarios further complicate the system design, requiring a rethinking of the existing system abstractions. 

In this talk, I will present my work on optimizing the modern x86 processor front-end. To that end, I will present my work on the micro-operation cache optimizations on a commercial-grade x86 processor that improved the x86 front-end throughput, reduced power consumption and the branch mis-prediction penalty. Following this, I will give a brief overview of my work on a hardware-software co-designed heterogeneous memory system that dynamically reconfigures based on the workloads executing on the system. Finally, in the last part of my talk, as part of my on-going and future research in secure memory architectures, I will present my work alleviating performance bottlenecks imposed by the existing security constructs.

Biography: Jagadish Kotra is a researcher at AMD Research (in Austin), where he is currently working on a variety of research topics including Heterogeneous CPU-GPU HPC systems, Processing-In-Memory architectures, and Secure Memory Architectures. He received his Ph.D. from The Pennsylvania State University in 2017. His current research interests are in the areas of Secure Memory Architectures, Memory Systems, Computer Architecture, Operating Systems, and Hardware-Software co-design. Jagadish’s work has appeared in several top-tier research venues like ASPLOS, MICRO and SIGMETRICS. He is an (co-) inventor on more than 20 patents that are either granted or under filing in the US Patent Office (USPTO) from his stints at various industry labs. For more information, check out his website: https://jbk5155.github.io/.